Three-Layer Integration Enhances CMOS Image Sensor Performance with AI Boost

CEA-Leti, a research institute in France, has made significant strides in the field of image sensor technology by developing a groundbreaking process that combines hybrid bonding and high-density through-silicon vias (TSVs) to integrate artificial intelligence (AI) into CMOS image sensors.

This innovative integration of AI by CEA-Leti has paved the way for a new generation of CMOS image sensors (CIS) that have the ability to leverage all image data for scene perception, situational understanding, and intervention.

The project involved the creation of a three-layer test vehicle featuring two embedded Cu-Cu hybrid-bonding interfaces (face-to-face and face-to-back) and one wafer containing high-density TSVs. These details were recently presented at the ECTC 2024 conference in Denver, showcasing advancements in stacking three 300 mm silicon wafers.

The demand for smart sensors is rapidly increasing due to their high-performance imaging capabilities in various devices such as smartphones, digital cameras, automobiles, and medical equipment. Manufacturers are faced with the challenge of enhancing sensor performance without compromising device size to meet the growing need for improved image quality and functionality enhanced by embedded AI.

Renan Bouis, a researcher at CEA-Leti in Grenoble, emphasized the significance of stacking multiple dies to create 3D architectures like three-layer imagers, which has revolutionized sensor design. He highlighted the importance of advanced interconnection technologies, such as hybrid bonding, for enabling seamless communication between different tiers and enhancing the performance of 3D-stacked architectures.

CEA-Leti's collaboration with EV Group has led to the establishment of a common lab focused on wafer bonding technologies, further advancing research in this area. The combination of hybrid bonding and HD TSVs in CMOS image sensors offers a pathway for integrating various components with precision and compactness, including image sensor arrays, signal processing circuits, and memory elements.

Eric Ollier, project manager at CEA-Leti and director of IRT Nanoelec’s Smart Imager program, highlighted the importance of these technological advancements in manufacturing 3D, multilayer smart imagers capable of addressing new applications that require embedded AI. The integration of hybrid bonding with HD TSVs in CMOS image sensors opens up possibilities for developing smart sensors with edge AI for high-performance semantic segmentation and object-detection applications.

Stéphane Nicolas, a researcher involved in the project, emphasized that the test vehicle represents a significant milestone in demonstrating the feasibility of each technological component and the integration process flow. The successful development of a fully functional three-layer, smart CMOS image sensor with edge AI capabilities marks a major achievement in the field of imaging technology.

CEA-Leti's continuous innovation was evident in their recent work on a two-layer test vehicle that showcased a 6-micron high HD TSV, resulting in improved electrical resistance and isolation performance compared to previous iterations. The optimized thinning process and reduced substrate thickness contributed to a 40 percent decrease in electrical resistance, enhancing voltage withstand capabilities.

With these advancements, CEA-Leti has solidified its position as a global leader in the development of next-generation smart imagers. The integration of edge AI in sensor technology is expected to revolutionize the imaging field, enabling enhanced performance and unlocking a myriad of new applications.

Sources: CEA-Leti, IRT Nanoelec