imec Demonstrates CFET Devices for 0.7nm Chip Designs

Belgian research lab imec has recently achieved a significant milestone in semiconductor technology by demonstrating the first electrically functional CMOS complementary FET (CFET) devices with stacked bottom and top source/drain contacts. CFET devices are considered a promising candidate for next-generation process technologies below 1nm, offering potential advancements in transistor design and performance.

These CFET devices consist of two transistors stacked on top of each other, each featuring an 18nm gate length, 60nm gate pitch, and 50nm vertical separation between n and p devices. The electrical functionality of these devices was successfully showcased on a test vehicle containing nFET and pFET devices with a common gate, and top and bottom contacts connected from the front side.

While the initial CFET devices were constructed with both contacts patterned from the front side, imec has also demonstrated the feasibility of relocating bottom contact formation to the back side of the wafer. This strategic move has significantly enhanced the top device survival rate from 11% to an impressive 79%, marking a substantial improvement in device reliability.

The imec roadmap envisions the integration of CFET devices in the A7 (0.7nm) node device architectures, building upon the foundation laid by the first description of CFETs back in 2018. This collaborative effort between imec, Intel, TSMC, and ARM underscores the importance of innovation and partnership in advancing semiconductor technology.

At the 2024 VLSI Symposium, imec unveiled the proposed process flow for sub-nm stacked CFET transistors, highlighting two CFET-specific modules: the middle-dielectric isolation (MDI) and the stacked bottom and top contacts. The MDI module, a pioneering innovation by imec, plays a crucial role in isolating top and bottom gates and fine-tuning threshold voltage settings for n and p devices.

Naoto Horiguchi, Director of CMOS device technology at imec, emphasized the effectiveness of an MDI-first approach in achieving optimal process control. By implementing innovative techniques such as source/drain recess etching with 'in-situ capping,' imec has successfully streamlined the fabrication process for CFET devices, ensuring precision and efficiency.

Another key module in the CFET fabrication process is the formation of stacked source/drain bottom and top contacts, separated by dielectric isolation. Overcoming challenges related to bottom contact resistance, imec's research team has explored the possibility of transitioning bottom contact formation to the wafer backside, a move that has shown promising results in enhancing device reliability and performance.

As imec continues to push the boundaries of semiconductor technology, the industry eagerly anticipates the widespread adoption of CFET devices and the transformative impact they will have on future electronic devices and systems.