Disabling IoT Transmitters: Power Cut

Researchers in Japan have made a groundbreaking advancement in the field of wireless communication for the Internet of Things (IoT). A team at the Institute of Science Tokyo has successfully developed a technique that could potentially eliminate a power-hungry block from wireless transmitters, paving the way for more efficient IoT devices.

At the heart of this innovation is the removal of the COordinate Rotation DIgital Computer (CORDIC), a key block in traditional transmitters. By combining three cutting-edge techniques, the researchers have demonstrated a novel approach to transmitter design at the prestigious ISSCC conference in the United States.

The rapid expansion of the IoT has created a pressing need for power-efficient transmitters, especially as the majority of IoT devices are battery-operated. Additionally, the growing integration of artificial intelligence (AI) is leading to higher data rates and increased power consumption, further underscoring the importance of energy-efficient communication technologies.

Traditionally, transmitters encode input data in polar coordinates, specifically amplitude and phase, which are then transmitted by precisely adjusting the output radio wave's polar coordinates. However, the reliance on CORDIC for determining these polar coordinates has posed challenges in terms of power consumption and data rate optimization.

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The innovative technique proposed by the Japanese researchers involves the use of Delta-Sigma Modulators (DSMs) to re-encode input data, resulting in a significant reduction in the bit count. By converting input signals into 3-level signals, the researchers were able to streamline the process of determining amplitude and phase values, leading to enhanced efficiency and performance.

One of the key advantages of this new approach is the elimination of linearity issues that commonly plague traditional modulation schemes. By quantizing the amplitude signal to 1 bit and leveraging a unique phase modulation technique, the researchers were able to achieve complete linearity in the transmitter's amplitude and phase control, without compromising on power efficiency.

Through rigorous testing and implementation using a state-of-the-art 65nm CMOS process, the team demonstrated superior power efficiency and data rates compared to existing transmitter designs. Professor Kenichi Okada expressed optimism about the potential impact of these advancements, emphasizing the significance of their CORDIC-less polar transmitter architecture in shaping the future of IoT communication.

These remarkable findings were presented at the 2025 IEEE International Solid-State Circuits Conference (ISSCC), marking a significant milestone in the evolution of wireless communication technologies.