Cadence validates 12.8 Gbps DDR5 MRDIMM IP system

Cadence has introduced the first DDR5 12.8 Gbps MRDIMM Gen2 memory IP system on the TSMC N3 process, catering to the increasing demand for enhanced memory bandwidth to meet the requirements of AI processing in enterprise and data center applications, particularly in cloud-based AI scenarios.

The newly unveiled 12.8 Gbps DDR5 MRDIMM IP features a cutting-edge architecture that is high-performance, scalable, and adaptable, drawing from Cadence’s successful DDR5 and GDDR6 product lines.

This Gen2 DDR5 IP comprises a PHY and a high-performance controller, forming a comprehensive memory subsystem. Through hardware validation using the latest MRDIMMs (Gen2), it achieves an impressive data rate of 12.8 Gbps, effectively doubling the bandwidth of current DDR5 6400 Mbps DRAM components. The DDR5 IP memory subsystem is constructed on Cadence’s proven high-performance architecture, incorporating ultra-low latency encryption and industry-leading RAS features. The DDR5 MRDIMM Gen2 IP is engineered to support advanced SoCs and chiplets with versatile floorplan design options, while the innovative architecture allows for precise power and performance optimization based on specific application needs.

“The Cadence DDR5 IP portfolio, in conjunction with Micron’s cutting-edge 1γ (1-gamma)-based DRAM, meets the escalating demand for increased memory bandwidth, density, and reliability to cater to AI processing workloads. These memory advancements play a crucial role in facilitating the next wave of AI/ML and HPC applications in data center and enterprise settings,” stated Praveen Vaidyanathan, vice president and general manager of Micron’s Data Center Products.

Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence, highlighted the substantial performance benefits that data center and enterprise applications can derive from Cadence’s DDR5 12.8 Gbps MRDIMM IP system. He noted that major customers are turning to Cadence to leverage this innovative technology, emphasizing the significant impact this cutting-edge memory IP system can have on next-generation SoC and chiplet products, ensuring their relevance for years to come.

The DDR5 controller and PHY have undergone verification using Cadence’s Verification IP (VIP) for DDR, streamlining the IP and SoC verification process for swift closure.