MIPI C-PHY Update for Image Sensor Applications

The MIPI Alliance has recently announced the update of its high-performance, low-power, and low EMI C-PHY interface specification, specifically designed for connecting cameras and displays. The latest version, MIPI C-PHY Version 3.0, introduces a new 18-Wirestate mode encoding option, which boosts the maximum performance of a C-PHY lane by around 30 to 35 percent. This enhancement allows for speeds of up to 75 Gbps over short channels, catering to the increasing demands of ultra-high-resolution and high-fidelity image sensors.

One of the key features of the updated specification is the introduction of a more efficient encoding option known as 32b9s. This option enables the transportation of 32 bits over nine symbols while maintaining the industry-leading low EMI and low power characteristics of C-PHY. For camera applications, the 32b9s mode offers flexibility by supporting lower symbol rates or lane counts for existing use cases, as well as higher throughput with current lane counts to accommodate new use cases involving very high-end image sensors.

The use cases for the new C-PHY encoding option are diverse and include next-generation prosumer video content creation on smartphones, machine vision quality control systems for fast-moving production lines, and advanced driver assistance systems (ADAS) that operate in challenging lighting conditions. These applications highlight the versatility and adaptability of MIPI C-PHY in meeting the evolving needs of various industries.

MIPI C-PHY plays a crucial role in supporting the MIPI Camera Serial Interface 2 (MIPI CSI-2) and MIPI Display Serial Interface 2 (MIPI DSI-2) ecosystems in low-power, high-speed applications across mobile, PC compute, and IoT platforms. The specification offers high throughput, a reduced number of interconnect signals, and superior power efficiency for connecting cameras and displays to application processors, making it an ideal choice for a wide range of devices.

Furthermore, the updated C-PHY specification enables lanes to be relocated within a link, functions as an embedded clock link, and allows for low-latency transitions between high-speed and low-power modes. The inclusion of an alternate low power (ALP) feature and fast lane turnaround capability enhances the flexibility of C-PHY, supporting asymmetrical data rates and optimising transfer rates based on system requirements. Additionally, the compatibility of MIPI C-PHY with MIPI D-PHY on the same device pins enables the development of dual-mode devices, further expanding the possibilities for designers.