AI enabled tool boosts chip interconnect

Arteris has recently introduced its latest AI-enabled tool for network-on-chip (NoC) interconnect IP, known as FlexGen. This innovative tool is designed to significantly enhance chip design efficiency by up to 10 times, streamlining the process and reducing design iterations from weeks to mere days. The incorporation of AI heuristics in FlexGen results in a remarkable reduction of wire length by up to 30% and latency by 10%, ultimately improving power efficiency in various applications such as automotive, datacenter, consumer electronics, communications, and industrial sectors, where chips typically contain between 5 and 20 NoCs.

FlexGen is built upon the foundation of the FlexNoC 5 NoC IP technology and component library, which are known for their physical awareness. By leveraging AI-driven automation, FlexGen minimizes manual adjustments by over 90%, enabling the rapid generation of optimized NoC topologies within hours instead of days. This tool offers support for custom topologies, empowering designers to tailor the interconnect structure to meet specific performance requirements and achieve a 10% latency reduction alongside improved bandwidth. The ability to swiftly iterate NoC IP alternatives facilitates early performance analysis during the initial stages of project planning.

One of the key features of FlexGen is its support for a wide range of industry-standard protocols, including AMBA 5 ACE-Lite, AHB, and AXI, which enhances scalability. The tool also provides built-in physical awareness, offering floorplan visualization and automatic timing closure assistance to enhance layout quality and productivity. By utilizing multiple NoC IP alternatives, designers can reduce interconnect area, optimize die size, and create space for integrating additional IP blocks, thereby improving overall chip efficiency.

Dream Chip Technologies has already adopted FlexGen to expedite their design process, reducing design iterations from weeks to days and enabling rapid experimentation and development. Jens Benndorf, the general manager of Dream Chip Technologies, praised FlexGen for its ability to automate NoC IP generation, allowing for the creation of adaptive topologies tailored to complex automotive traffic requirements within minutes. The tool has enabled the company to achieve superior power, performance, and area (PPA) metrics, leading to faster SoC delivery with enhanced quality.

Industry leaders have also expressed their enthusiasm for FlexGen. John Rayfield, corporate vice president of AI Silicon at AMD, commended Arteris for developing this smart NoC technology, emphasizing its potential to support next-generation product innovation. Charles Janac, president and CEO of Arteris, highlighted the significance of FlexGen in addressing the design challenges faced by semiconductor companies and system houses. With its ability to reduce design time and enhance quality of results, FlexGen is poised to drive faster innovation cycles and deliver superior products in the electronics industry.

For more information about FlexGen and its capabilities, visit arteris.com/FlexGen.