AI Performance Skyrockets with Optical Interconnect Technology

Wafer-scale processor developer Cerebras is making significant strides in enhancing the performance of its systems through the development of an optical substrate, which is expected to boost performance by a factor of 4000. The company is actively seeking collaboration within the industry and advocating for standardization to drive innovation forward.

The current Cerebras WSE3 processor, constructed on a single 300mm wafer with 900 million transistors and consuming 20kW of power, required the company to create its own wafer-scale packaging for I/O, power delivery, and cooling. Now, the focus has shifted towards the implementation of an optical interconnect to further improve system efficiency.

During the Leti Innovation Days in Grenoble, France, JP Fricker, co-founder and chief system architect at Cerebras, discussed strategies to address scalability challenges using chiplet and 3D heterogeneous packaging technologies. Fricker emphasized the potential of these techniques for transformative advancements in the field.

One of the critical factors impacting performance, scalability, and power consumption is the off-chip I/O. Fricker highlighted the significance of I/O in large-scale computing systems and the necessity to develop innovative technologies to integrate them effectively. The ultimate goal is to create supercomputers that are 4000 times faster than current systems by connecting 1000 wafers together.

Fricker also stressed the importance of optimizing the distribution of I/Os across the chip surface to enhance efficiency. By reducing channel length, the size of SERDES can be minimized, resulting in space and power savings. The vision includes incorporating a substantial number of optical engines within the chip to facilitate multiple communication lanes at data rates of 100 to 200Gbit/s.