Cerebras Harnesses Optical Interconnect for 4000x AI Enhancement

Wafer-scale processor developer Cerebras is making strides in enhancing the performance of its systems by a significant factor of 4000 through the development of an optical substrate. The company is actively seeking collaboration within the industry and advocating for standardization to drive innovation forward.

The current Cerebras WSE3 processor, constructed on a single 300mm wafer housing 900 million transistors and consuming 20kW of power, required Cerebras to create its own wafer-scale packaging for I/O, power delivery, and cooling. Now, the California-based company is focusing on implementing an optical interconnect to further improve its processor's capabilities.

During the Leti Innovation Days in Grenoble, France, JP Fricker, co-founder and chief system architect at Cerebras, discussed strategies for addressing scalability challenges using chiplet and 3D heterogeneous packaging technologies. Fricker emphasized the potential of these techniques for transformation within the industry.

Fricker highlighted the critical role of off-chip I/O in determining performance, scalability, and power consumption. He explained, "I/O is a limitation in big compute and prevents you from achieving very large systems. While the necessary technologies currently exist, there is a need to innovate and integrate them effectively. Our objective is to develop technologies that will enable the creation of supercomputers that are 4000 times faster than current systems, with up to 1000 wafers interconnected."

Looking ahead, Cerebras aims to incorporate a substantial number of optical engines into its processors. Fricker envisions integrating these engines directly onto the chip surface for enhanced communication capabilities at data rates ranging from 100 to 200Gbit/s. This approach would involve distributing I/Os across the chip to optimize space and power efficiency.