DRAM memory without the capacitor shows promises

A breakthrough in DRAM technology has been achieved with the development of a new bit cell design that eliminates the need for a capacitor and instead utilizes two thin-film transistors. This innovation, presented in a recent report by imec, offers promising solutions for advancing the DRAM technology roadmap.

The traditional DRAM bit cell consists of a capacitor and a silicon-based transistor, with the capacitor storing charge and the transistor facilitating access to the stored data. While this design has served as the foundation for DRAM technology for many years, it has faced challenges in terms of scalability, cost, and power efficiency.

Since around 2015, the DRAM industry has encountered difficulties in keeping up with the performance improvements seen in processor logic. Issues such as the constraints imposed by the large capacitor and the increasing leakage path in access transistors have hindered the scalability and efficiency of DRAM technology.

However, in 2020, imec introduced a novel DRAM bit cell concept that addresses these challenges effectively. This new design features two thin-film transistors for read and write operations, eliminating the need for a capacitor altogether. The transistors are made of an oxide semiconductor like indium-gallium-zinc-oxide (IGZO), which offers low off current and benefits retention time, refresh rate, and power consumption.

By utilizing thin-film transistors and eliminating the capacitor, this new DRAM bit cell design overcomes the limitations of traditional 1T1C cells. The use of IGZO-based transistors ensures a longer retention time, reducing the need for frequent refreshing of DRAM cells and improving power efficiency. Additionally, the absence of a large capacitor allows for enhanced scalability and 3D integration, paving the way for high-density DRAM solutions.