Embedded RISC-V CHERI core for automotive

Codasip in Germany has developed a customisable RISC-V core for automotive applications that uses the CHERI memory-safe architecture.

The L370 configurable 32bit 32-bit, in-order, dual-issue, 9-stage pipeline RISC-V core includes safety mechanisms and security features for ISO/SAE 21434 and ISO 26262 compliance up to the ASIL D integrity level. This comes from support for safety mechanisms such as Data redundancy (ECC), parity on AXI interface and Dual Core Lock Step.

The core is available in a range of high-quality, pre-verified, baseline configurations that can be further configured and customized through risk-free custom instruction extensions. This is made possible by a new level of customization in the Codasip Studio Fusion tool called  Bounded Customization.

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The core can be extended with new instructions without risk because the functionality of the baseline core is guaranteed in all cases via defined bounds and formal methods. Codasip Studio Fusion generates a verification framework that substantially simplifies the verification of the custom instructions.

Depending on their specific needs and the results of software application profiling performed in Codasip Studio Fusion, engineers can either configure the core from a defined set of pre-verified options, create custom instructions within set bounds, or design freely.

The Studio Fusion tool can then automatically generate an SDK (Software Development Toolkit) including a compiler, simulation models, debugger, and profiler, and an HDK (Hardware Development Kit) including RTL (Register Transfer Level) and a verification framework.

The core is highly configurable, allowing different performance points in the real time embedded space, including local memories for low-latency access, an integrated Core Local Interrupt Controller (CLIC), configurable branch prediction and support for single and double precision floating point instructions as well as the CHERI architecture.

It is compliant with RISC-V RV32IMAFDCZcb Interfaces and includes a 64bit AXI5-Lite Memory Manager Interface and Core Subordinate Interface for Tightly Coupled memories (TCM) and RAS Error Record Register Interface (RERI) access.

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“The automotive industry is increasingly looking to RISC-V to solve its needs for innovation while elevating technical and commercial control through ownership,” said Jamie Broome, chief product officer at Codasip. “Trust is the key challenge we face in this sector, and it is therefore crucial to work with a vendor that understands this and also offers unique possibilities for innovation. Our Custom Compute approach provides exactly this. We recognize the importance of combining leading design methodology with best-practice safety mechanisms, advanced security features, and verified core quality,”

More details of the Codasip L730