Graphene in CMOS process for 2D interconnect

A US startup has achieved wafer-scale synthesis of high-quality graphene within a 300mm CMOS wafer process.

California-based Destination 2D says this is the first two-dimensional (2D) material in mainstream semiconductor products.

Under linewidths of 15 nm, the resistivity of copper interconnect increases rapidly, causing significant degradation in both circuit and system-level performance, power, and dramatically impacting all reliability metrics required by modern semiconductor designs in products such as GPUs, CPUs and others.

Large area graphene synthesis typically involves chemical vapour deposition (CVD) which requires high temperatures that far exceed the allowed thermal budget of CMOS interconnect fabrication, and also require a mechanical transfer of the graphene grown over a metallic substrate to dielectric substrates.

Pristine monolayer graphene is a semi-metal with a low charge carrier density, resulting in high sheet resistance, which further limits its direct applicability to interconnect applications. Therefore, for interconnect applications, multiple layers of edge-contacted graphene along with suitable intercalation-doping is required.

This was first theorized and experimentally demonstrated by Destination 2D’s CTO Prof Kaustav Banerjee and his team at US Santa Barbara, who subsequently pioneered the pressure-assisted solid-phase diffusion technique for synthesizing multilayered graphene directly over dielectric substrates at CMOS-compatible temperatures.

Destination 2D’s CMOS-compatible interconnect design innovation is achieved via intercalation-doped and edge-contacted multi-layer graphene, which delivers lower resistivity, significantly better reliability and up to 80% higher energy-efficiency than copper interconnects.

A CMOS-compatible synthesis technology allows for the direct synthesis of graphene onto wafer-scale dielectric substrates at temperatures significantly below the CMOS thermal budget. All of this is achieved without the warping and cracking issues that have plagued previous graphene commercialization efforts around CMOS interconnects. 

All this led to Destination 2D being co-founded by Bannerjee with Ravi Iyengar as CEO, a semiconductor microprocessor design veteran turned serial entrepreneur.

An equipment engineering team led by Chief Product Officer Dave Silvetti is working on several cutting-edge CMOS process technology equipment designs into high-volume production, starting with CoolC GT300 which is also launching. This implements Destination 2D’s proprietary graphene synthesis process without the traditional thermal issues that have prevented graphene from being in CMOS applications.

“Wafer-scale graphene coverage demonstrated by Destination 2D using BEOL compatible low-temperature transfer-free process marks a significant milestone for the CMOS industry,” said Ravi Iyengar, CEO of Destination 2D. “Destination 2D’s interconnect technology – when integrated in both Logic and Memory chips – could profoundly transform the landscape for Artificial Intelligence and other compute-centric applications.”