Intel and TSMC to Unveil 2nm Processes at IEDM

In a recent publication, researchers at TSMC are gearing up to reveal the innovative N2 manufacturing process, a groundbreaking nominal 2nm process specifically tailored for applications in AI, mobile devices, and high-performance computing. Coinciding with this announcement, Intel engineers are set to divulge intricate details about scaling RibbonFETs, the proprietary nanosheet transistors developed by Intel.

During the upcoming IEDM conference, experts from TSMC are anticipated to present findings showcasing the remarkable capabilities of the N2 process. It is projected that N2 will deliver a notable 15 percent increase in processing speed or a substantial 30 percent reduction in power consumption, all while enhancing chip density by at least 15 percent compared to its predecessor, the N3 process introduced in 2022.

The cross-sectional view of the N2 interconnect stack, featuring a copper redistribution layer, exemplifies the seamless integration of the N2 platform with cutting-edge 3D technologies. This integration is expected to revolutionize the landscape of semiconductor manufacturing, paving the way for more efficient and powerful computing solutions.

Furthermore, a paper titled "2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC, and Mobile SoC Applications," authored by G. Yeap and team from TSMC, will showcase an SRAM macro boasting a world-record density of 38Mbits per square millimeter. The paper will delve into the intricacies of middle- and back-end-of-line interconnects, highlighting the scalable copper-based redistribution layer and other key features aimed at enhancing performance and reliability.

According to the researchers, the N2 platform has already met stringent wafer-level reliability standards and is on track for full qualification by 2025, with mass production slated to commence in 2026. This timeline underscores the rapid pace of innovation in the semiconductor industry and the relentless pursuit of technological advancement.

On a parallel front, in a separate presentation titled "Silicon RibbonFET CMOS at 6nm Gate Length," A. Agrawal and colleagues from Intel will showcase their prowess in building nanosheet technology with 6nm gates and a 45nm contacted polysilicon pitch. The team will demonstrate how they have maintained electron mobility without degradation, a critical achievement in the realm of semiconductor design.

The authors of the Intel paper will shed light on the Drain-Induced Barrier Lowering (DIBL) phenomenon and its correlation with silicon thickness, offering valuable insights into the optimization of transistor performance. Their focus on nanosheet scaling underscores Intel's commitment to pushing the boundaries of semiconductor technology and staying at the forefront of innovation.