JEDEC, the global leader in the development of standards for the microelectronics industry, recently disclosed exciting details about its forthcoming standards for DDR5 Multiplexed Rank Dual Inline Memory Modules (MRDIMM) and a cutting-edge Compression-Attached Memory Module (CAMM) for LPDDR6. These new modules are poised to transform the industry by offering unmatched bandwidth and memory capacity.
DDR5 MRDIMMs represent a significant leap forward in memory module design, aimed at boosting data transfer rates and overall system performance. By leveraging multiplexing technology, these modules can combine multiple data signals and transmit them over a single channel, effectively enhancing bandwidth without the need for additional physical connections. This seamless upgrade in bandwidth will empower applications to surpass the data rates achievable with DDR5 RDIMMs.
The JEDEC MRDIMM standard is projected to deliver up to double the peak bandwidth of native DRAM, enabling applications to achieve unprecedented levels of performance beyond current data rates. Despite this significant enhancement in bandwidth, the standard maintains the same capacity, reliability, availability, and serviceability (RAS) features as JEDEC RDIMMs. The committee's goal is to double the bandwidth to 12.8 Gbps and elevate the pin speed, while also designing MRDIMM to support more than two ranks and ensuring compatibility with conventional RDIMM systems by utilizing standard DDR5 DIMM components.
Looking ahead, plans are in motion to introduce a Tall MRDIMM form factor that will provide increased bandwidth and capacity without necessitating changes to the DRAM package. This innovative form factor, which is taller in design, will enable twice the number of DRAM single-die packages to be mounted on the DIMM without the requirement for 3DS packaging, thereby optimizing space and efficiency.
Furthermore, as a follow-up to JEDEC's JESD318 CAMM2 Memory Module standard, the JC-45 committee is actively developing a next-generation CAMM module tailored for LPDDR6, targeting a maximum speed exceeding 14.4 GT/s. The planned module will feature a 24-bit subchannel, a 48-bit channel, and a connector array, underscoring JEDEC's commitment to pushing the boundaries of memory module technology.