Neural Networks Power Low-Power DPD for 5G Non-Linearity

As the carrier frequencies continue to rise and channel packing becomes denser in telecommunication systems, the demand for linearity in RF-PAs has become increasingly stringent. Traditionally, "Class A" designs have been favored for their superior linearity, albeit at the cost of power efficiency. However, modern modulation systems, especially in 5G networks, pose challenges due to high power ratios between symbols. While energy-efficient designs suffer from non-linearities, solutions like Doherty amplifiers fall short due to inherent non-linearity.

Advancements in high-speed digital signal processing have led to the development of digital pre-distortion (DPD) algorithms. These algorithms enable real-time correction of amplifier non-linearities by distorting the signal to compensate for the amplifier's response. While instrumental for 3G and 4G networks, current DPD approaches face challenges in 5G networks. Dense antenna arrays experience cross-talk issues, making it hard to obtain clean observation signals, exacerbated by increasing frequencies. Moreover, complex processing for each antenna element conflicts with the need for low-power solutions.

"We devised a solution based on established mathematical principles and neural network capabilities," explained Prof. Ludovico Minati, the leading inventor of the patent underlying the study. The team leveraged multi-layer neural networks to learn and invert the association between non-linear distortions and polynomial coefficients, offering a promising approach to non-linearity correction.

The latest RF-PAs based on CMOS technology exhibit simple, memory-effect-free responses, simplifying the DPD problem to determining polynomial coefficients quickly and stably for real-world operation. Dr. Aravind Tharayil Narayanan, the lead author, highlighted the development of a hardware architecture at Tokyo Tech's Nano Sensing Unit. This system autonomously calculates DPD coefficients based on minimal data, reducing cross-talk issues and design complexities.

Prof. Hiroyuki Ito, head of the Nano Sensing Unit, emphasized the minimal real-time processing and shared hardware benefits of their approach, maximizing power efficiency. The team collaborated with Fujitsu Limited to test the concept on cutting-edge hardware at 28 GHz, paving the way for large-scale implementation using ASIC designs. An international PCT application has been filed, with results published in IEICE Electronics Express, showcasing the potential of their innovative DPD technology.