Renesas 32bit RISC-V MCU: Integrated Code Generator

Renesas Electronics and Segger have joined forces to enhance the development process for the R9A02G021 group of 32-bit RISC-V microcontrollers. By integrating Segger Embedded Studio into the Renesas code generator, engineers now have access to end-to-end support for general purpose applications.

The Renesas Smart Configurator plays a crucial role in this collaboration, allowing design engineers to visually configure MCU peripherals like timers, interfaces, and interrupt controllers. This configuration process generates source code projects that are compatible with SEGGER Embedded Studio. Leveraging the powerful code optimization capabilities of the built-in C/C++ compiler and the advanced debug features of J-Link debug probes, engineers can expedite the development of their RISC-V designs.

According to Daryl Khoo, Vice President of the Embedded Processing 1st Business Division at Renesas, global ecosystem partnerships are essential for the success of new products. Khoo expresses excitement about the partnership with SEGGER, emphasizing the importance of providing customers with reliable and efficient development tools for Renesas' latest 32-bit RISC-V product. This collaboration aims to accelerate the adoption of RISC-V-based products in the market.

Rolf Segger, the founder of Segger, echoes the sentiment of collaboration by highlighting the company's commitment to supporting key silicon vendors in the dynamic RISC-V market. With Segger's Friendly License, Embedded Studio is available for non-commercial use at no cost, allowing users to evaluate its features without restrictions. The user-friendly interface, compact code size, fast execution speed, and other advanced functionalities have contributed to the growing popularity of Embedded Studio among end users and silicon vendors.

The SEGGER ecosystem for RISC-V development includes a range of tools such as Embedded Studio, a multi-platform IDE with a highly optimizing C/C++ compiler, the Ozone graphical debugger, SystemView real-time recording and visualization tool, and programming and debug support through the J-Link family of debug probes. Additionally, Segger's Flasher family of in-circuit programmers ensures high yield rates during the production phase, with programming support for the R9A02G021 group inherited from J-Link. The tools also facilitate programming external memories via the microprocessor.