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Spectre Enhances Cryogenic Memory with SPICE Model Calibration

June 21, 2024

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Semiwise and sureCore, two innovative companies based in the UK, have recently made significant strides in the field of quantum computing. By utilizing the Spectre tool from Cadence Design Systems, they have successfully tackled critical challenges in developing cryogenic CMOS circuits for quantum computer systems.

The collaboration between Semiwise and sureCore focused on modifying transistor models on GlobalFoundries 22FDX using the Cadence Spectre Simulation Platform. This platform is renowned for its capabilities in analog, mixed-signal, and digital circuit simulation and verification at cryogenic temperatures, making it an ideal choice for this cutting-edge project.

Part of the Innovate UK project for the Development of CryoCMOS, this endeavor marked a significant milestone in the quest to enable the next generation of scalable quantum computers. Semiwise, based in Scotland, spearheaded the development of robust transistor SPICE models specifically designed to operate in extreme cryogenic environments. This breakthrough has the potential to revolutionize quantum computing by increasing the number of qubits within a system and enhancing computational capabilities for solving complex real-world problems.

Professor Asen Asenov, CEO of Semiwise, highlighted the importance of the project, stating, "We were able to develop production-worthy designs for cryogenic CMOS circuits by leveraging cryogenic transistor measurements and a leading commercial TCAD simulator. This enabled us to create high-quality compact transistor models that account for corners and mismatch, essential for the success of our endeavor."

sureCore's contribution to the project involved the development of low-power SRAM cells capable of operating at near absolute zero temperatures required by quantum computer systems. These SRAM cells, which can function from 77K (-196°C) downwards, have been re-characterized for cryogenic operation, ensuring compatibility with industry-standard physical design flows from RTL to GDSII.

Paul Wells, CEO of sureCore, emphasized the challenges in designing memory elements for cryogenic environments, stating, "The bit cell, a critical storage element, must be treated as an analog circuit highly sensitive to process variability and mismatch. Our focus on running extensive statistical circuit simulations is crucial for guaranteeing the yield and reliability of our IP."

Tom Beckley, senior vice president and general manager of Cadence's Custom IC & PCB Group, expressed excitement about the collaboration, saying, "We are thrilled to work with Semiwise and sureCore in developing models within the Spectre Simulation Platform for cryogenic CMOS circuits. The availability of calibrated SPICE models for cryogenic environments marks a significant advancement in the field."

The project also involved Agile Analog in Cambridge and Siemens EDA, further enhancing the collaborative effort towards advancing cryogenic CMOS technology for quantum computing. The first 22FDX SRAM cryogenic memory tapeout by sureCore is currently underway, validating re-characterized standard cells and a range of embedded memory IP.

Sources: Semiwise, sureCore, Cadence

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