Survey shows decline in first-time-right IC design

A recent global survey of 597 design verification engineers and executives has revealed a concerning trend - a significant decrease in first-time-right IC designs in 2024. The data shows that only 14 percent of IC designs are proven correct on the initial pass, a notable drop from 26 percent in 2012 and 32 percent in 2012.

Commissioned by Siemens Digital Industries Software and carried out by the Wilson Research group, the survey had a diverse pool of participants from various regions. North America, Europe (including Turkey and Israel), India, and East Asia accounted for 31%, 26%, 11%, and 29% of the respondents, respectively, with an additional 3% from other geographies.

The report emphasizes the growing complexity of IC and ASIC design, citing the integration of embedded processors and analog circuits, as well as the heightened focus on security and safety requirements. While logical and functional design errors continue to be the primary contributors to design respins, the percentages in these categories have either stabilized or decreased compared to previous years.

On the rise are errors related to yield, reliability, safety, and security, indicating a shifting landscape in the challenges faced by design verification engineers. Projects utilizing formal verification and advanced verification systems have shown to experience fewer design respins, although the debugging of verification scripts remains a significant time-consuming task for engineers.

As a result, the demand for verification engineers is on the rise, with some demanding segments seeing a ratio of 5 verification engineers to 1 design engineer. This highlights the critical role that verification engineers play in ensuring the success and quality of IC designs in an increasingly complex and challenging environment.