Synopsys supports Intel 18A-P, E process tech

Synopsys and Intel Foundries have collaborated to develop production-ready design flows for the 18A and 18A-P higher performance process technologies. These cutting-edge technologies are set to enter volume production later this year, catering to 1.8nm designs utilizing RibbonFET gate all around (GAA) transistors and introducing the first backside power delivery architectures.

Furthermore, the companies are actively engaged in early design technology co-optimization for the Intel 14A-E efficient lower power process. This collaboration is the outcome of an extensive design technology co-optimization (DTCO) effort between Intel Foundry and Synopsys engineering teams.

Notably, Synopsys has optimized its IP for Intel 18A and expanded support for Intel 18A-P designs. The Intel 18A process boasts a 15% improvement in performance per watt compared to the previous 3nm technology, along with a 30% area enhancement. The 18A-P variant is expected to further enhance performance, while the 18-E version will focus on increasing density.

On the customer front, there is a growing interest from military clients in the Intel 18A technology. Intel has already commenced sampling the Panther Lake processor on the 18A platform. Additionally, Aion Silicon has recently joined the Intel Foundry Accelerator Design Service Alliance, signaling a broader industry collaboration.

The AI-enabled EDA reference flow for 18A and 18A-P offers a unified exploration-to-signoff platform that accelerates 2.5D/3D multi-die designs for Intel’s Embedded Multi-die Interconnect Bridge-T (EMIB-T) chiplet packaging technology. This solution aligns with the objectives of the Intel Foundry Accelerator Chiplet Alliance and the Intel Foundry Accelerator Design Service Alliance.

EMIB-T represents a convergence of EMIB 2.5D and Foveros 3D packaging technologies, enabling high interconnect densities beyond the reticle limit. The EMIB-T reference flow facilitates early bump and TSV planning and optimization, incorporating automated UCIe and HBM routing for enhanced efficiency.

John Koeter, Senior Vice President of the Synopsys IP Group, emphasized, “Our production-ready EDA flows, IP, and multi-die solution provide our mutual customers with comprehensive technologies to accelerate the development of chip designs that meet or exceed their requirements.” In response, Suk Lee, VP & GM of Ecosystem Technology Office at Intel Foundry, highlighted the collaborative efforts, stating, “Our continued collaboration with Synopsys enables engineering teams to accelerate ‘systems of chips’ innovation utilizing our unique systems foundry capabilities and optimized Synopsys EDA flows and IP on Intel 18A and Intel 18A-P process nodes to create differentiated designs with faster time-to-results.”

Lastly, Synopsys IP and EDA flows have been fine-tuned for power and area optimization on the Intel 18A and Intel 18A-P process nodes, leveraging the benefits of PowerVia backside power through thermal-aware analysis. The IP offerings on the Intel 18A process node encompass a wide range of components, including 224G Ethernet, PCIe 7.0, UCIe, USB4, embedded memories, logic libraries, IOs, and PVT sensors, catering to diverse design requirements.