Universal Verification Methodology for Mixed-Signal designs approved  

The Accellera Systems Initiative has approved the Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 standard and made it available to download free of charge (see link below). 

The UVM-MS 1.0 standard is a comprehensive and unified analog/mixed-signal (AMS) verification methodology based on the IEEE 1800.2 UVM standard. This enhances the verification of AMS and digital/mixed-signal (DMS) integrated circuit designs and systems. It defines a robust framework for the creation of AMS verification components and testbenches by extending digital-centric UVM classes and enabling interaction between class-based and structural environments.

• Federated simulation standard working group formed
• The evolving world of verification

The objective of the Working Group was to standardize a method for driving and monitoring mixed-signal nets within UVM including stimulus, score-boarding and analysis, creating  mixed-signal verification components by extending existing digital-centric verification IP.

To do this, UVM-MS 1.0 introduces the concept of the MS Bridge, a SystemVerilog module that connects UVM agents to mixed-signal DUTs. This bridge includes an MS Proxy class, which provides an API to control the bridge core. The MS Bridge Core handles datatype conversions and signal manipulations, ensuring accurate modeling of analog behaviors. This comprehensive approach standardizes methods for driving and monitoring mixed-signal nets within UVM, significantly enhancing the productivity and quality of verification processes for AMS and DMS designs.

“The strong industry interest in this standard underscores its importance. As an organization devoted to improving design and verification productivity for both users and vendors, we eagerly anticipate its positive impact on the industry,” said Lu Dai, Chair of Accellera.

“The release of UVM-MS 1.0 is a game changer for the verification of AMS designs,” said Tom Fitzpatrick, Chair of the Working Group that put the UVM-MS standard together. “This unified approach will help to make the verification of components and subsystems much more efficient and enable the development of reusable UVM-MS verification components, similar to Verification IP available today in UVM for digital verification.”

The long-term goal for the standard is to transition it to the IEEE Design Automation Standards Committee (DASC) for formal standardization for ongoing maintenance, greater adoption, and sustained development of the standard worldwide.

Details of the UVM-MS standard are on the UVM-MS Working Group page is available for immediate download fee free.