05/08/2019, hardwarebee
JTAG stands for Joint Test Action Group. It is essentially a standard that is used for verification, testing, and exploration of PCBs (Printed Circuit Boards) after they have been manufactured. It is an interface that gives you a channel to communicate with and control the chips on the circuit board of a particular piece of hardware. This interface also allows you to debug your hardware in real time by allowing you to directly take control of the clock cycles through software.
JTAG was introduced in the 1980s in order to make testing of printed circuit boards relatively easier and more thorough. Since then, the JTAG interface is now being used for all sorts of purposes, including programming, debugging, as well as testing. It is connected to an on-chip Test Access Port, or the TAP that allows it to access a set of test registers. These registers present chip logic levels and the abilities of the device being tested.
The purpose of a boundary scan using JTAG on a printed circuit board is to be able to test the interconnects present between the various ICs or chips on the board without having to get or use a physical test probe. The main advantage of this scan is that you do not have to gain physical access to the pins but can still read the values and analyze them however needed.
In this test, the signals between the core logic of the hardware and the pins are being intercepted by a serial scan path called the BSR, or the Boundary Scan Register. This register consists of a plethora of boundary scan cells which are considered to be invisible when the device is in operation. These cells can, however, be modified to either set or read the value off of the pins of the device. As such, the BSR can be used to test as well as debug the device as you are given control over the states of the pins.
Normally, the JTAG interface is connected to the board or the chip using a number of pins in a four plus one formation, with the latter being optional. These are also the signals that are used by TAP to conduct the boundary scan.
TCK – Test Clock
This is the signal that is responsible for the synchronization of the internal state of the machine operations.
TMS – Test Mode Select
At the rising edge of the Test Clock, the Test Mode Select signal is sampled in order to determine what the next state will be.
TDI – Test Data In
This is the signal that is sampled at the rising edge of the clock signal when the internal state machine finds the correct state, and represents the data that is sent into the logic of the device or hardware at question.
TDO – Test Data Out
Similarly, this signal is sampled at the falling edge of the clock signal when the internal state machine is in the correct state and is a representation of the data that so shifted out of the logic of the subject hardware.
TRST – Test Reset
This is an optional pin. This synchronous/asynchronous active pin can be used to reset the test logic.
