Advanced Imaging: 3D Multi-Layer Stacking

3D integration has revolutionized the way multiple functions can be combined within a confined space, leading to enhanced performance while minimizing power consumption. This technology has seen significant progress in various areas such as 3D stacked memories, chiplets, and heterogeneous integration. However, in recent times, complementary metal-oxide semiconductor (CMOS) imager sensors (CIS) have emerged as the frontrunners in the realm of 3D integration.

One of the key trends in emerging image sensing technologies is the adoption of 3D multi-layer stacking. The existing 2-layer based imagers have already reaped the benefits of 3D hybrid-bonded stacking methods, enabling the amalgamation of two separately optimized technologies: dedicated pixel technology (low noise, high dynamics, high quantum efficiency) and advanced analog and digital CMOS (high-density, low-power).

Advancing further in multi-layer integration, the addition of a third layer becomes pivotal. The concept of three-layer integration is particularly intriguing as it not only allows for the separate optimization of individual layers but also provides additional silicon for implementing new functions, innovative partitioning solutions, or utilizing different advanced technology nodes.

These three-layer approaches play a significant role in the ongoing pixel shrink race while upholding optical performances. Moreover, they open up possibilities for directly embedding artificial intelligence (AI) and memory within the sensor itself. The development of technologies for this new generation of smart imagers with embedded AI is underway at CEA-Leti as part of the IRT Nanoelec/Smart Imager Program, which involves key industry players such as STMicroelectronics, Siemens EDA, Prophesee, Lynred, and Grenoble INPUGA.

The program addresses various challenges, ranging from innovative architectures to the design and implementation of silicon technologies. The combination of hybrid bonding and high-density through-silicon vias (HD TSVs) holds promise for integrating the different components of imagers seamlessly. CEA-Leti's silicon technology advancements, including wafer-to-wafer hybrid bonding and HD TSVs, have showcased significant progress with key demonstrations of 2-layer and 3-layer integrations, setting the stage for the next era of smart imagers.