Breakthrough: First 3nm UCIe Chiplet IP Unveiled with TSMC CoWoS Packaging

Alphawave Semi has made a significant advancement in the realm of semiconductor technology by developing a cutting-edge 3nm chiplet IP designed for the UCIe standard, marking a groundbreaking achievement for TSMC's CoWoS packaging technology.

The innovative multi-protocol subsystem IP created by Alphawave boasts an impressive 8 Tbit/s/mm bandwidth density for die-to-die connections, offering a data rate of 24 Gbit/s tailored for hyperscalers, HPC, and AI devices manufactured at TSMC.

One of the key highlights of Alphawave's development is the successful implementation of the PHY and controller IP in 3nm silicon, specifically optimized for TSMC's Chip-on-Wafer-on-Substrate (CoWoS) 2.5D chiplet packaging technology, which leverages a silicon interposer. This achievement is a first in the industry and showcases Alphawave's pioneering approach.

The versatile PNY supports various streaming protocols, including the PCIe and CXL standards within the UCIe framework, as well as AXI-4, AXI-S, CXS, and CHI system-on-chip bus specifications to ensure seamless interoperability across the chiplet ecosystem. Additionally, it integrates live per-lane health monitoring for enhanced reliability and enables operation at 24 Gbps, meeting the high bandwidth demands for die-to-die connectivity.

"Achieving successful silicon bring-up of the 3nm 24 Gbps UCIe subsystem with TSMC's advanced packaging represents a significant milestone for Alphawave Semi, highlighting the company's expertise in harnessing the TSMC 3DFabric™ ecosystem to deliver top-tier connectivity solutions," stated Mohit Gupta, Alphawave Semi's Senior Vice President and General Manager of Custom Silicon and IP.

Alphawave Semi recently finalized its acquisition of OpenFive, a move that complements its RISC-V capabilities and enhances its chiplet portfolio. The UCIe subsystem IP from Alphawave aligns with the latest UCIe Specification Rev 1.1 and incorporates a range of testability and debug features, including JTAG, BIST, DFT, and Known Good Die (KGD) capabilities.

This latest launch builds upon Alphawave's previous milestones, including the introduction of the first 3nm silicon with standard packaging earlier this year and the unveiling of the industry's inaugural multi-protocol chiplet in June. These achievements underscore the company's commitment to innovation and its strategic acquisition of OpenFive for its expertise in chiplet design and development.

For more information on Alphawave Semi's die-to-die PHY IP and its advancements in chiplet technology, visit Alphawave Semi's official website.