IEDM: CFETs make progress at 5nm and 7angstrom

Researchers from TSMC, IMEC, IBM and Samsung are all due to report on progress vertically-stacked complementary field effect transistors (CFETs) at this year’s International Electron Devices Meeting (IEDM) coming up in December, in San Francisco.

Engineers from foundry TSMC have a paper on the performance of a fully functional monolithic CFET inverter made on a 48nm gate pitch. A 48nm gate-pitch is roughly equivalent to a 5nm process

The CFET, a concept originally proposed by the IMEC research institute, is thought to be the transistor architecture to come after the gate-all-around multi-channel transistors.

Paper 2.5, entitled First Demonstration of Monolithic CFET Inverter at 48nm Gate Pitch Toward Future Logic Technology Scaling is authored by S. Liao et al form TSMC.

The inverter a building block for many logic circuits is made from n-type nanosheet transistor stacked above a p-type nanosheet transistor. The TSMC includes backside contacts and interconnect for improved performance and increased design flexibility.

The devices made at TSMC exhibit voltage transfer characteristics up 1.2V and subthreshold slope of 74 to 76mV/V for both n- and p-type devices. This performative CFET is described as milestone in the progress of CFET technology even though it is unlikely to be inserted into commercial manufacturing at contemporary nodes. The area reduction achieved by two-transistor stacking is accompanied by manufacturing process complexity, however further dimensional scaling and stacking in a manner similar to 3D-NAND could give rise to advances in power, performance, area, and cost (PPAC).

Paper 2.4 is presented by researchers from IMEC and the title – Double-Row CFET: Design Technology Co-Optimization for Area Efficient A7 Technology Node – suggest continued progress in scaling CFETs higher in the z direction and in the x-y plane. The A7 or 7angstrom technology node is expected to follow the 1nm (A10) node. IMEC’s own roadmap in the past has had CFETs entering mainstream production at the A5 node in about 2032.

IMEC is also engaged using contemporary process nodes. Paper 2.7 discusses direct backside contact to both source and drain in a 60nm gate-pitch process, roughly equivalent to a 7nm node.

IBM Research and Samsung are also participating in CFET exploration with Paper 2.8 –Monolithic Stacked FET with Stepped Channels for Future Logic Technologies.

This paper puts forward the idea of a stepped structure where the bottom FET channels are wider than those above. The benefit is a reduced stack height and less challenges from high aspect ratio processes. The paper also includes discussion of top-bottom channel middle dielectric isolation, top-bottom source/drain isolation and dual work function metals. The precis does not discuss a metal or gate pitch so readers will have to wait for the presentation or proceedings to understand more.

IEDM conference takes place December 7 to 11, 2024 at the Hilton San Francisco Union Square hotel, with online access to recorded content available afterward.