IEDM: Samsung speeds selection of selector-only memory materials

Samsung has used computer modelling to accelerate the selection of a material system for selector-only-memory (SOM). Researchers are due to present a paper on the work at this year’s International Electron Devices Meeting (IEDM) coming up in December, in San Francisco.

SOM is a promising novel memory that offers non-volatility along with DRAM-like read/write performance and stackability.  

SOM builds on cross-point memory architectures, where memory are made from arrays of stacked electrodes crossing over one another. Phase-change memory and RRAM arrays both use this approach, which conventionally requires a selector transistor or diode such as a germanium-selenide ovonic threshold switch (OTS).  The selector serves a key role in that it selects the memory cell being addressed and prevents “sneak paths” through the array that would bypass the selected cell. 

In recent years researchers have explored the possibility of using a chalcogenide-based selector not only as the selector but also as the memory itself, thus creating a novel non-volatile memory option.

Thus far research on SOM has simply used available amorphous chalcogenide materials made from mixtures of Ge, As and Se. But other chalcogenides are available and Samsung asserts it could identify more than 4,000 chalcogenide combinations that could potentially offer denser, faster, more reliable and power-efficient SOM devices.

The classical approach of comprehensive laboratory-based physical chemistry and electronic measurement would require significant time and expense and so Samsung turned to computer modelling to predict the potential of various material combinations.

In Paper 17.1, Ab-initio Screening of Amorphous Chalcogenides for Selector-Only Memory (SOM) through Electrical Properties and Device Reliability, H.-J. Sung et al., are due to set out how they reduced a field of 4,888 to 18 thus leaving a more reasonable number for physical investigation.

By investigating threshold voltage drift and the drift of the memory window – the voltage difference between a device’s ‘on’ and ‘off’ states – as they simultaneously optimized selector and memory characteristics, they established key screening parameters.

The modelling included assessments of bonding characteristics, thermal stability, electrical properties and device reliability. It is hoped that the paper will discuss the possibility that discrete combinations could show unexpected beneficial behaviour that could be missed by the modelling approach.

Samsung had a paper at IEDM 2023 which reported on a 64Gbit OTS-based SOM with a memory cell dimension of 16nm.

IMEC explains

In the following paper in the same session at IEDM Sergiu Clima from the IMEC research institute is scheduled to present two possible mechanisms to explain the operation of OTS in the selector-only memory (SOM).

An IMEC research group has authored Paper 17.2 Selector Only Memory: Exploring Atomic Mechanisms from First-Principles including simulations of two possible atomistic mechanisms that could lead to mobility gap changes and hence threshold voltage modulation, which determines the memory window of SOM.

The first mechanism is local atomic bond rearrangement and the second is atomic segregation. The work confirms previous high-level modelling assertions about the working principles of OTS and SOM, the authors claim.

IEDM conference takes place December 7 to 11, 2024 at the Hilton San Francisco Union Square hotel, with online access to recorded content available afterward.