JEDEC releases LPDDR6 targeting mobile and AI

The JEDEC Solid State Technology Association has recently unveiled the latest Low Power Double Data Rate 6 (LPDDR6) standard, known as JESD209-6. This new standard is set to revolutionize memory speed and efficiency across various applications, such as mobile devices and AI systems. With enhanced performance, power efficiency, and security features, LPDDR6 represents a significant advancement in memory technology.

One of the key highlights of LPDDR6 is its dual sub-channel architecture, which enables flexible operation while maintaining a small access granularity of 32 bytes. The standard introduces several new features to optimize channel performance capabilities, including 2 sub-channels per die, 12 data signal lines (DQs) per sub-channel, and four command/address (CA) signals per sub-channel. These enhancements aim to improve data access speed and reduce ball count.

LPDDR6 also offers a Static Efficiency mode designed to support high-capacity memory configurations and maximize bank resource utilization. The standard includes on-the-fly burst length control to accommodate 32B and 64B access, as well as Dynamic write NT-ODT for adjusting ODT based on workload demands, thereby enhancing signal integrity.

In terms of power efficiency, LPDDR6 operates with a lower voltage and lower power consumption VDD2-capable supply compared to its predecessor, LPDDR5. The standard incorporates features like alternating clock command inputs, Dynamic Efficiency mode, and Dynamic Voltage Frequency Scaling for Low Power (DVFSL) to minimize power consumption during low-frequency operation.

Security and reliability have also been prioritized in LPDDR6, with features such as Per Row Activation Counting (PRAC) for DRAM data integrity, Carve-out Meta mode for system reliability, and support for programmable link protection scheme and on-die error correction code (ECC). Additionally, LPDDR6 offers support for Command/Address (CA) parity, error scrubbing, and memory built-in self-test (MBIST) to enhance error detection and system reliability.

Mian Quddus, Chairman of the Board of Directors at JEDEC, expressed pride in the development of LPDDR6, attributing its success to the dedicated efforts of the JC-42.6 Subcommittee for Low Power Memories. With its blend of power efficiency, security options, and high performance, LPDDR6 is poised to be the preferred choice for next-generation mobile devices, AI systems, and other power-conscious applications seeking optimal performance.