Lauterbach teams for virtualised RISC-V in automotive

Lauterbach and hypervisor developer Kernkonzept are working together on virtualised development environment for RISC-V systems.

Kernkonzept and Lauterbach have worked on a RISC-V development and debug environment for RISC-V software with a virtualized software architectures on the QEMU emulation platform.

A software architecture for Software Defined Vehicles (SDV) for example combines cloud technologies with automotive functional safety and real-time requirements for the first time, with the consequence that virtualization is indispensable. Leading semiconductor suppliers in the automotive value chain have already committed to the open RISC-V instruction set architecture. However corresponding SoCs, which will enable virtualization on RISC-V CPUs, are still under development.

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To execute mixed-critical workloads with different security levels on a high-performance processor, strong isolation including the respective operating systems is essential. To achieve this, developers can virtualize the underlying hardware with the help of a hypervisor so that workloads with different safety levels are executed in isolated Virtual Machines (VMs).

Kernkonzept’s open source L4Re Hypervisor runs on the Generic RISC-V Virtual Platform implemented in QEMU, while Lauterbach’s TRACE32 debug and trace tools allow the analysis of the entire software stack including the L4Re Hypervisor itself and all virtual machines (VM) with their heterogeneous OSes and applications.

This allows developers of virtualized software architectures and applications running on heterogeneous rich and real-time OSes can start their development work before the corresponding RISC-V chips are delivered in silicon. Kernkonzept’s L4Re Hypervisor securely separates real-time workloads even on very small chips. The minimal code base in privileged mode and all its possibilities for integrating security and safety functions perfectly into the system make the L4Re Hypervisor family ideal for products that must be certified.

Using these features reduces the risk in the certification process while also saving time and resources for the automotive industry, avionics, or the IoT. TRACE32 enables simultaneous debugging and of the CPU and other cores in an emulated or silicon SoC, a unique capability that covers the entire system.

On a virtualized system, the TRACE32 Hypervisor-aware debugging allows to perform concurrent OS-aware debugging for each guest OS/virtual machine (VM) and display an overview of the overall system. The TRACE32 tools provide access to hypervisor and OS structures and data so developers can better understand how they are behaving and utilizing chip resources.

“We are excited to enable the development of virtualized software architectures on RISC-V together with Kernkonzept”, said Norbert Weiss, Managing Director of Lauterbach. “Virtualization is the key to Software Defined Vehicles, where multiple safety-critical and non-critical applications are sharing a platform and thanks to our collaboration, developers can start creating world-class software immediately”, said Adam Lackorzynski, Founder and CTO at Kernkonzept.