SiFive Enhances RISC-V AI Processor IP with Matrix Engine

SiFive, a leading provider of RISC-V processor IP, has introduced the XM Series, featuring a matrix engine and custom extensions tailored specifically for edge AI applications. This marks the first time SiFive has incorporated such advanced features into their IP, catering to the growing demand for AI capabilities in various sectors.

The XM Series IP is designed to cater to a wide range of applications, including Edge AI and IoT chips, consumer devices, next-generation electric and autonomous vehicles, as well as data centers. With a highly scalable AI matrix engine, the XM Series aims to deliver superior performance and efficiency for AI workloads in diverse environments.

One of the key highlights of the XM Series is the integration of scalar, vector, and matrix engines to tackle the memory bandwidth challenges commonly faced in AI designs. Each cluster of the XM Series comprises four X-Cores, each equipped with dual vector units, enabling a cluster to achieve impressive performance metrics of up to 16 TOPS (INT8) or 8 TFLOPS (BF16) per GHz.

Moreover, SiFive has announced its plans to open source a reference implementation of the SiFive Kernel Library (SKL), further enhancing the accessibility and customization options for developers working with RISC-V architecture. This move is expected to foster collaboration and innovation within the RISC-V community.

Patrick Little, CEO of SiFive, emphasized the advantages of leveraging an open processor standard in the rapidly evolving AI landscape. He highlighted SiFive's commitment to providing energy-efficient solutions and empowering customers to tailor their products to meet specific requirements, underscoring the company's strengths in performance per watt.