SiFive Expands into Datacentre AI Processor IP with RISC-V

SiFive, a leading provider of RISC-V processor IP, has recently unveiled the P870-D datacentre RISC-V IP, a modified version of its high-end P870 core. This new variant is designed to offer increased scalability for datacentre AI chip designs, with the capability to scale up to an impressive 256 cores. In addition to the enhanced scalability, the P870-D incorporates a range of new features specifically tailored for datacentre AI applications.

The P870-D processor supports various industry-standard protocols, including the open AMBA CHI protocol, Compute Express Link (CXL), and CHI chip-to-chip (C2C) communication for heterogeneous system-on-chip (SoC) and chiplet configurations. SiFive has also collaborated with Arteris to implement network-on-chip (NoC) solutions, featuring a distributed and scalable IOMMU for accelerating virtualized device IO. These advancements are crucial for meeting the latest functional safety and security requirements in datacentre environments.

Moreover, the P870-D comes equipped with advanced Reliability Availability Serviceability (RAS) features aimed at detecting errors proactively to safeguard data integrity. By identifying potential issues before they escalate, these RAS capabilities help minimize downtime and enhance the overall reliability of the system, ensuring uninterrupted operation for critical datacentre applications.

According to Ian Ferguson, senior director at SiFive, the P870-D represents the company's inaugural venture into a datacentre-specific core. He emphasized the significance of energy efficiency in the design, highlighting the inclusion of a CPU, vector engine, and matrix maths that can seamlessly scale up to 256 cores, a substantial leap from the previous 16-core limit on a single chip or chiplets.

In addition to the core's RAS features, the P870-D boasts support for larger 57-bit virtual memory through the Sv57 extension and hardware virtualization for hypervisors using the RVA23 RISC-V extensions. Ferguson underscored the importance of collaborating with third-party partners to align with evolving trends in technologies like HBM, emphasizing the critical role of software development in maximizing the potential of chip architectures.