Category Archives: FPGA Design

Understanding FPGA Logic Synthesis

06/08/2019, hardwarebee

Today, the process of logic synthesis plays a very integral and crucial role in the creation and execution of FPGAs and in ensuring that they work optimally and with high efficiency. Logic synthesis, as suggested by the name, is a process of converting high level logic design into gates.
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Xilinx Hits Milestone with First Customer Shipments of Versal ACAP

18/06/2019, hardwarebee

Xilinx, Inc. (NASDAQ: XLNX), the leader in adaptive and intelligent computing, today announced that it has shipped Versal™ AI Core series and Versal Prime series devices to multiple tier one customers through the company’s early access program. Versal is the industry’s first adaptive compute acceleration platform (ACAP), a revolutionary new

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Logic Design Solutions Introduces the first NVMe Host IP on PolarFire FPGA

11/06/2019, hardwarebee

France, Gournay sur Marne — June 11th 2019 – Logic Design Solutions (LDS) extends its portfolio of NVME-HOST IPs with the first NVME-HOST IP on POLARFIRE FPGA which enables designers to address specific market in embedded recording domain.
Higher performance
MVMe disks can manage several PCIe links, which allows them

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FPGA Power-On-Reset Design and Implementation

08/06/2019, hardwarebee

fpga internal structure

Power-On Reset is an electronic circuit that generates a reset pulse, which sets the entire design to an initial and well-known state after the power supply is detected. In Vivado the Xilinx’s Processor System Reset LogiCORE IP provides this functionality.

If a synchronous reset is executed at system

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Verilog vs. VHDL – What to Choose?

16/05/2019, hardwarebee


The world of HDL (Hardware Description Language) is divided between Verilog vs VHDL. Some believe that Verilog is best suited for ASIC and FPGA development and some believe that VHDL is a much more superior programing language. This debate has been carrying on since the past few decades. And it

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CEO Talk – Sven Meier of NetTimeLogic

01/05/2019, hardwarebee

This interview was held with Sven Meier, CEO of NetTimeLogic GmbH.

Tell me a bit about your background? How did you first get started with NetTimeLogic?
I worked for many different companies where FPGAs, time synchronization and network redundancy were always key technologies. I have a

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