Synchronous and asynchronous counters are the two widely used counters in digital circuits. In this article, the difference between synchronous and asynchronous counter are discussed in detail including their characteristics, applications and operation are meticulously written.

Counters are the simplest form of sequential circuits and flip-flops are the basic building blocks of sequential circuits. Flip-flops are connected together to form counters. Apart from counting, counters can be used to measure some fundamental quantities like time, frequency, memory addresses etc.

In this article we will use an example of a three-bit binary counter to discuss the difference between synchronous and asynchronous counter . This is a binary counter, and it is capable of counting in binary sequence (that is 1’s and 0’s). It is capable of counting from 000)₂ to 111)₂. This counter resets itself and back to 000)₂ when it is reached to the maximum count. For an ‘N’-bit counter, ‘N’ number of flip-flops are required, and hence it is capable of counting up to 2^N-1. For example, an 8 bit binary counter has 8 flip-flops and can count up to 2⁸ – 1 = 256 – 1 = 255. Or in binary format, it can count from 00000000)₂ to 11111111)₂ and then reset. Designing an N-bit counter is easy — just add a flip-flop for every additional stage.

Asynchronous Counters

These counters are made up of a series of flip flops that are connected in series or back to back. The clock is applied to the first flip flop only. The second flip-flop is triggered by the transition that occurs at the output of the first flip-flop. Similarly, the clock input of the third flip-flop is triggered by the output of the second flip-flop and so on. Their operation and implementation are straightforward tasks, and hence minimum hardware is required. Each flip-flop is triggered by the previous flip-flop, as a result, the speed of operation is limited. The delay problem arises for the following reasons: The clock is applied to the first flip-flop and triggered FF0. This change cannot be felt by flip-flop FF1 immediately because of the propagation delay through the first flip-flop (FFO). Similarly, there is a propagation delay through FF1, after a delay, FF2 will be triggered. The effect of the input clock pulse is slowed downed, and after some delay, the change is felt by the last flip-flop. These types of counters are called series or ripple counters.

3-Bit Binary Asynchronous Counter

A 3-bit counter consists of three flip-flops and has 8 states. It can count from 000)₂ to 111)₂.

To observe the output of the counter, let’s apply 8 pulses to the CLK input of the first flip-flop (this is LSB) and observe the output at Q₀, Q₁ and Q₂. Both J and K inputs are connected to logic HIGH. All flip-flops are positive edge triggered.

Initial condition:

Q₀ = 0

Q₁ = 0

Q₂ = 0

CLK1:During the positive-going edge of CLK1 Q₀ goes high and Q₀‘ goes LOW. Q₀‘ is connected to the CLK input of Q₁ but it has no effect because a positive-going transition is required to trigger the flip-flop FF1.

Q₀ = 1

Q₁ = 0

Q₂ = 0

CLK2:During the positive-going edge of CLK2 Q₀ goes LOW and Q₀‘ goes HIGH. This is the positive-going transition and the flip-flop FF1 is all set to trigger.

Q₀ = 0

Q₁ = 1

Q₂ = 0

CLK3: This time Q₀ goes HIGH again. Q₀‘ goes LOW. It will not trigger FF1. So, FF1 remains in its state.

Q₀ = 1

Q₁ = 1

Q₂ = 0

CLK4: This time Q₀ goes LOW. Q₀‘ goes HIGH. There is a transition that occurs in FF1. So, FF1 changes from 1 to 0. Q₁‘ goes from 0 to 1 for the first time. This is a positive-going edge. Now FF2 is ready to change its state.

Q₀ = 0

Q₁ = 0

Q₂ = 1

CLK5: Q₀ goes HIGH. Q₀‘ goes LOW. No changes occur in FF1 and FF2.

Q₀ = 1

Q₁ = 0

Q₂ = 1

CLK6: Q₀ goes LOW. Q₀‘ goes HIGH. This time FF1 changes its state.

Q₀ = 0

Q₁ = 1

Q₂ = 1

CLK7: Q₀ goes HIGH. Q₀‘ goes LOW. No changes occur in FF1 and FF2.

Q₀ = 1

Q₁ = 1

Q₂ = 1

What will happen in the next clock pulse?

Q₀ goes LOW. Q₀‘ goes HIGH. This time FF1 changes its state from high to low. Q₁‘ goes high. There is a positive-going edge for FF2. FF2 changes its state from high to low. All three flip-flops are reset to zero.

Q₀ = 0

Q₁ = 0

Q₂ = 0

Synchronous Counters

These counters are made up of a series of flip flops, synchronized with the same clock signal. All of the flip-flops change their state simultaneously with a single clock pulse – at the same time.  Synchronous counters work at a much higher frequency than their counterpart’s ripple counters, as there is no cumulative delay between the two flip-flops.

3-Bit Binary Counter:

To observe the output of the counter let’s apply 8 clock pulses. Examine the waveforms at output Q₀, Q₁, and Q₂. Assume all flip-flops are positive edge triggered.

Initial condition

Assume that the counter is in a binary 0 state. And all flip-flops are RESET.

Q₀ = 0

Q₁ = 0

Q₂ = 0

CLK1: When the positive edge of the first clock pulse appears, FF0 toggles. Q₀ goes HIGH. Remember all flip-flops receive clock pulses at the same time. FF1 gets its J and K input from Q₀. J₁ and K₁ inputs are low during CLK1 because Q₀ has not gone high immediately. There is a propagation delay from triggering and propagating to the output Q₀.

Q₀ = 1

Q₁ = 0

Q₂ = 0

CLK2: When this clock pulse occurs, FF0 toggles and Q₀ goes LOW. FF1 toggles its state and Q₁ goes HIGH after some delay. Due to this propagation delay between clock pulse and output transition, FF2 remains in its initial state.

Q₀ = 0

Q₁ = 1

Q₂ = 0

Delay

J₁ = 1

K₁ = 1

CLK3: When this clock pulse occurs, FFO toggles its state, and Q₀ goes HIGH. FF1 remains in its previous state. FF2 remains LOW because there is an AND gate connected. When Q₀ and Q₁ outputs are HIGH, then the transition will occur in FF2.

Q₀ = 1

Q₁ = 1

Q₂ = 0

Delay

J₁ = 1

K₁ = 1

J₂ = 1

K₂ = 1

CLK4: This time FF2 is ready to change its state. Q₂ goes HIGH. FF0 toggles Q₀ and goes LOW. FF1 toggles and goes LOW.

Q₀ = 0

Q₁ = 0

Q₂ = 1

CLK5: During the positive-going edge of this clock, FF0 toggles, and Q₀ goes HIGH. FF1 and FF2 remain in their previous state.

Q₀ = 1

Q₁ = 0

Q₂ = 1

Delay

J₁ = 1

K₁ = 1

CLK6: During the positive-going edge of this clock, FF0 toggles, and Q₀ goes LOW. FF1 toggles and Q₁ goes HIGH. and FF2 remains in its previous state.

Q₀ = 0

Q₁ = 1

Q₂ = 1

Delay

J₁ = 0

K₁ = 0

CLK7: During the positive-going edge of this clock, FF0 toggles, and Q₀ goes HIGH. FF1 and FF2 remain in their previous state.

Q₀ = 1

Q₁ = 1

Q₂ = 1

Delay

J₁ = 1

K₁ = 1

CLK8: When this clock pulse occurs, FF0 toggles Q₀ goes LOW. FF1 toggles Q₁ goes low as well. Q₀ and Q₁ are at the input of an AND gate. The output of the AND gate goes LOW as well. All the flip flops are RESET again.

Difference Between Synchronous and Asynchronous Counters

The table below summarizes the difference between synchronous and asynchronous counters: