The History of Verilog

Verilog is a hardware description language also known as IEEE 1364. It is used in modeling electronic systems and devices. Often used in the creation and verification of digital circuits when used at the register-transfer level as part of the abstraction of the process e.g. ASIC and FPGA design.

An example for AND gate implementation using Verilog:

module and2 (c, b, a);

output c; // module outputs

input a,b; // module inputs

assign c = a&b; // continuous assignment

endmodule

In its original form, Verilog was intended to describe and simulate the automated synthesis of language subsets. After the language created started spreading, it expanded to include structures such as gates which is how Verilog is used today.

One of the first hardware description languages to be created, Verilog was the brainchild of Prabhu Goel, Chi-Lai Huang, Douglas Warmke, and Phil Moorby. Working over the winter of 1983 to 1984, the team created Verilog using their own experience in similar systems. Chi-Lau Huang had helped to foster the LALDS hardware description.

The success of VDHL caused Cadence to make the move to expand Verilog for open standardization by transferring it to the public domain. This move created the organization Accellera which was originally known as Open Verilog International. The Verilog became IEEE Standard 1346 – 1995 or Verilog-95 as it was known.

Called the Automated Integrated Design Systems, the company that had been formed was purchased by Cadence Design Systems in 1990. Today, Cadence retains all property rights to the Verilog and Verilog-XL design originated by the Gateway Design Automation company. The success of the Verilog-95 led to numerous advances over the next several years. In addition, the Verilog-A was created as a support to Spectre, an analog simulator, although it was never intended to be a language that stood by itself.

The next major step occurred six years later when a new Verilog system was sent to the IEEE that offered improvements to the system. Called the IEEE 1364-2001, it is better known as the Verilog-2001. Most of the upgrades included support for variables and signed nets, a smoothing out of the signed operations process that helped to improve overall performance. In addition, there was control over the statement instantiation which also improved the process significantly.

In 2005, another improvement was made to the Verilog system, although it was not as dramatic a leap from the Verilog-95 to the Verilog-2001. The Verilog-2005 offered some new language features and clarified some spec and other aspects of the design to make it run smoother. In addition, the Verilog-AMS was developed to bring together both mixed and analog sound modeling and incorporate it into the traditional Verilog system.

An example for 8 bit up counter implementation using Verilog:

module up_counter_8bit   (out, enable, clk, clock Input, reset); 

output [7:0] out;

input enable,

clk, reset;

reg [7:0] out; 

always @(posedge clk)

if (reset) begin

out <= 8’b0 ;

end else if (enable) begin

out <= out + 1;

end

 endmodule

Since the Verilog-2005, there now the SystemVerilog, an update that was made with new capabilities and features which help in design verification and modeling. The SystemVerilog-2009 represents a combination of both Verilog and SystemVerilog standards and the current version is known as IEEE 1800-2017.

Over the years, Verilog has established itself as one of the most popular of all hardware descriptive languages thanks to its robust features and expanding platform. There is little doubt that Verilog will continue to be a force in the industry fo,r the foreseeable future.