FPGA to ASIC Conversion Guide

This article will help you understand the steps required in converting your FPGA to an ASIC. The world of electronics and circuitry continues to grow and evolve every day, making significant process with each new advent and invention. When it comes to hardware, especially considering integrated circuits, it plays a key and central role in the development of the simplest as well as the most complex piece of technology that we may use in our day to day or in very specific industrial applications. This step to step guide will help you with your FPGA to ASIC conversion.

What is an FPGA?

FPGAs are only one of the most widely known and frequently used semiconductor chips that are programming circuits in a specific configuration for a particular application. FPGA is well known as Field Programmable Gate Array and it essentially acts as a programmable IC.

FPGAs are typically made up of a couple of Configurable Logic Blocks (CLBs). Each logic block comprises of a programmable logic device which can be configured by the user. The configurable logic blocks are then connected to each other with the help of routing interconnects fabric.

FPGAs vs. ASICs

ASIC stands for Application Specific Integrated Circuit, and as suggested by the name, these are circuits that are dedicated to a particular purpose or to accomplish a certain task since their manufacturing process. These are usually rigid and cannot be reprogrammed like FPGAs, as they are permanently hardened in silicon. ASICs are much better suited for high volume applications than FPGAs.

FPGAs, on the other hand, find their applications all across the field, included among them are video and images, medical and science, aerospace and defense, telecom and datacom, server and cloud, etc. they are availed in data manipulation tasks as well as in the field of commerce and for the sake of enabling automation in any given workplace.

FPGAs are preferred for low volume production purposes where a small number of highly specific and flexible solutions are needed for an application. However, when it comes to mid or high volume circuit production as well as low cost and low power consuming solutions, then ASICs come out on top. An ASIC is very specific in its design, formatted only to accomplish a predefined task, and is hence smaller in size and highly functional in regards to what it is meant to achieve.

THE NEED TO PERFORM FPGA TO ASIC CONVERSION

FPGA to ASIC conversion is a possibility for several companies in the industry thanks to the benefits it brings. With the help of FPGA to ASIC conversion, it has become possible to extract the advantages of both- the flexibility and developmental benefits of FPGAs, and the superior size and power consumption of ASICs.

This means that the circuit would initially be designed as an FPGA, and then be converted into an ASIC through a cost effective yet extremely efficient process. Many companies turn to FPGA to ASIC conversion to capitalize on the cost improvement and competitive advantage it brings to the table. The conversion also improves the time to market for the products, ensuring that your company gets the competitive edge over others in your niche. You ship your first product with an FPGA and when you reach to high volume, you can replace the FPGA with an ASIC. An ASIC based solutions leads to lower power consumption, smaller size and lower unit cost.

FPGA TO ASIC CONVERSION PROCESS

As FPGA design is merely an RTL code, this allows engineers to use a traditional ASIC design flow: Logic synthesis, floorplanning, synthesis and layout.

The following are the requires steps based on an article from AnySilicon.com

ASIC Design Flow Step 1: Logic Synthesis

• RTL conversion into netlist
• Design partitioning into physical blocks
• Timing margin and timing constrains
• RTL and gate level netlist verification
• Static timing analysis

ASIC Design Flow Step 2: Floorplanning

• Hierarchical ASIC blocks placement
• Power and clock planning

ASIC Design Flow Step 3: Synthesis

• Timing constrains and optimization
• Static timing analysis
• Update placement
• Update power and clock planning

ASIC Design Flow Step 4: Block Level Layout

• Complete placement and routing of blocks

ASIC Design Flow Step 5: ASIC Level Layout

• ASIC integration of all blocks
• Place and route
• GDSII creation