Cutting-Edge Timing Chip Boasts 25fs Jitter

Renesas Electronics has introduced a new family of timing chips designed for wireline infrastructure, data center, and industrial applications. The FemtoClock 3 devices are equipped with low power consumption and 25fs jitter, meeting the demands of 112Gbps SerDes rates and future 224Gbps SerDes designs. These chips operate on a single 1.8V supply and integrate non-volatile memory for customization at no extra cost to the customer.

The highly integrated FemtoClock 3 devices can generate up to four frequency domains and feature integrated LDOs with superior PSRR, reducing board complexity and cost. With multiple operating modes in a single chip, the clock tree design is simplified, making it ideal for high-speed interconnect systems in various applications such as telecom switches, data center switches, medical imaging, and broadcast audio & video.

Exceeding the next-generation SerDes reference clock requirements, the FemtoClock 3 offers 25fs-rms jitter and complies with ITU-T G.8262 and G.8262.1 for enhanced synchronous Ethernet. Renesas has already utilized the FemtoClock 3 in a reference design for a 1600G Fixed Form Factor Switch, showcasing its capabilities in real-world applications.

According to Zaher Baidas, Vice President of the Timing Division for Renesas, "FemtoClock 3 devices extend our leadership in timing solutions by providing multiple clock and synchronization functions in a single device with ultra-low jitter, simplifying PCB design and reducing solution area and cost." Vincent Ho, CEO at UfiSpace, also praised the FemtoClock 3 for its performance, low power dissipation, and PCB design simplicity, highlighting Renesas' ability to deliver cutting-edge timing solutions.

The FemtoClock 3 family is available in 7 x 7mm 48-pin VFQFPN and 9 x 9mm 64-pin VFQFPN packages, offering multiple operating modes including synchronization, jitter attenuation, and clock generation. Customers can combine the FemtoClock 3 solution with Renesas' ClockMatrix™, VersaClock, buffer, and oscillator portfolio to address complex timing requirements in wireline infrastructure and data center designs.