Gate Array is a technology that an engineer can use to design and then produce chips or ASICs. also referred to as Uncommitted Logic Arrays (ULAs) and semi-custom chips, the gate array approach allows for more flexibility and versatility. You have a prefabricated chip that comprises of all of the various components such as NAND gates and flip flops that are to be a part of your circuit board. All of these components are later connected together with the help of metal interconnect layers that are laid down during the manufacturing process. These gate arrays and chips are widely used in the design, production, and manufacturing of ASICs, or Application Specific Integrated Circuits.
You begin with a host of transistors on a chip. The transistors placed on the prefabricated chip serve no predefined function before the connections have been made between the various other components. The next step is to lay down metal layers that create bridges and connections between all of these checkpoints, ultimately forming many NAND and NOR logic gates. These logic gates are also interconnected with one another in unique pathways with the help of metal layering in the factory. The final layer of the metal is added at the very end of the manufacturing process so as to make the circuit functional and preserve its integrity and performance standard during the actual manufacturing process.
These master chip fabrication are usually produced in a stockpiled manner. Typically, the development and manufacturing of a chip using the gate array approach tends to reduce the time consumed in the overall process, finishing the job in a shorter time than what would be taken up in the production of a standard cell or a full custom design, and it also reduces the non recurring engineering mask costs as the number of custom masks produced is lowered.
When compared to other approaches for the development of ASIC chips, one of the few drawbacks of the gate array is the fact that they tend to have a lower density and relatively poor performance. But these negatives become irrelevant in particular scenarios, such as when there is a need for low production volumes. Other disadvantages include a larger cell size, are overhead due to unused transistor cells, as well as over dimensioned routing channels.
Other manufacturing processes that produce different products such as analog and structured arrays use similar designs and methodologies that may remind you of a gate array, but are not referred to as such. When the use of gate arrays became a thing in the world of ASIC chips early in its developmental history, high performance transistor transistor logic, emitter coupled logic, and current mode logic configurations were created using bipolar transistors. This bipolar ULA technology was introduced first in the United Kingdom by Ferranti, but the idea as later abandoned in favor of semi custom chips or the gate array approach.
Since the days of TTLs, ECLs, and CMLs, we have moved on to Complementary Metal Oxide Semiconductor gate arrays, or CMOS gate arrays, which are much more efficient their function and have become a commonplace tool in the ASIC manufacturing process across the industry. The very first CMOS gate arrays were produced and manufactured by International Microcircuits Inc. in 1974. The very first CMOS gate array product family produced by this group used 7.5 micron single level metal CMOS technology and had anywhere between 50 to 400 gates. This inspired design lead to the formation and development of many more modern and automated designs, including the n-channel and p-channel transistors, interconnects on grids as opposed to running with minimum custom spacing, and ultimately, 2 layer CMOS arrays which are now fully automated.
In the beginning, due to a lack of software applications and automated tools, chips were designed by hand drawing which had to be traced out and the processing layers were cut and peeled to create an enlarged representation of the circuit design. This was then photo reduced to a smaller mask.
The gate arrays of yore used to be low performing as well as space, time, and power consuming. Their application was largely limited to low power and portable products, and was only used in applications such as aerospace and other products that needed to be rushed to reduce the time to market. Gradually, however, gate arrays began to make progress by becoming more efficient and automating its processes, and its credibility rose when it was used in an IBM flagship mainframe CPU product in 1981.
The use of gate arrays is not as common today, since the product experiences an indirect competition with FPGAs and other programmable logic devices that did not need a semiconductor wafer foundry to deposit the interconnects and make the circuit functional. People are looking for flexible and customizable solutions that adapt to their requirements and give them the cost effectiveness and high standard performance they need for optimum device development and functioning. CPLDs and FPGAs enable individuals to do just that- creating interconnects in the field without having to worry about the proper factory resources to etch them out onto the wafer, and modifying circuit designs on the go as per their immediate needs.