Category Archives: FPGA Design

The Ultimate Guide to RTL Design

11/03/2021, hardwarebee

This article provides an overview of Register Transfer Level (RTL) Design, it describes the fundamentals of RTL design and the process of RTL design. The article will also discuss RTL synthesis, RTL for synchronous and asynchronous design, RTL simulation, RTL in FPGA and ASIC and RTL design tools.
 
What

The Ultimate Guide to FPGA Architecture

01/03/2021, hardwarebee

This article provides a closer look into the history and the current FPGA architecture and it intended for electronics, FPGA and software engineers that would like to learn more about FPGA internals. The article discusses the traditional FPGA architecture and modern FPGA architecture. Also, it discusses the usage of internal

FPGA Projects and (free) Source Code

03/02/2021, hardwarebee

This article covers FPGA projects from beginners to expert level. You can find here FPGA projects for engineering students, cool FPGA projects and FPGA projects used in commercial products. All FPGA projects are with free and downloadable source code, allowing you to use the projects at home or at work.

FPGA vs. Microcontroller, what to choose?

18/01/2021, hardwarebee

This article provides a comparison between FPGA vs. Microcontroller. We did the comparison between FPGA vs. Microcontroller by looking into their differences and similarities in terms of architecture, cost, performance, application, programmability technology, power consumption, processing capability and usability in the real-time world.
 
FPGA vs. Microcontroller
 
FPGA and

The Ultimate Guide to FPGA Test Benches

15/12/2020, hardwarebee

Creating test benches for your FPGA design is a critical step for any FPGA design project. This article is written for the FPGA verification design engineers who want to use VHDL as HDL verification language for designing and simulating of their FPGA based digital design.
 
The VHDL test benches

Promwad focuses on Zynq UltraScale+ custom projects as a Xilinx authorised design partner

30/11/2020, hardwarebee

Promwad has dedicated an engineering team to help its clients accelerate hardware product development based on Zynq UltraScale+ MPSoC devices and other systems-on-chip. The company’s portfolio now includes about a dozen completed designs with Zynq US+ modules, high-speed interfaces, Linux customization, and drivers development.
 
Xilinx Zynq empowers hardware and

AMD to Acquire Xilinx, Creating the Industry’s High Performance Computing Leader

27/10/2020, hardwarebee

SILICON VALLEY, Calif., Oct. 27, 2020 (GLOBE NEWSWIRE) — AMD (NASDAQ: AMD) and Xilinx (NASDAQ: XLNX) today announced they have entered into a definitive agreement for AMD to acquire Xilinx in an all-stock transaction valued at $35 billion. The combination will create the industry’s leading high performance computing company, significantly

How to Create an Efficient FPGA Development Environment

05/10/2020, hardwarebee

This document provides a starting point for an efficient FPGA development environment. This will be split into the following sections:
 

How to select a text editor for your FPGA project
How to manage an FPGA project over git
Introduction to Doxygen with VHDL projects
Additional resources

 
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Subaru Selects Xilinx to Power New-Generation EyeSight System

24/08/2020, hardwarebee

SAN JOSE, Calif.–(BUSINESS WIRE)– Xilinx, Inc. (NASDAQ: XLNX) today announced that its technology is powering the new version of Subaru’s vision-based advanced driver-assistance system (ADAS), EyeSight. Integrated into the all-new Subaru Levorg, the new EyeSight system will provide advanced features including adaptive cruise control, lane-keep assist and pre-collision braking, putting best-in-class safety

10 Top Mistakes in FPGA Programming

14/07/2020, hardwarebee

This document provides a list of ten mistakes that are common in FPGA programming. We have collected 10 top mistakes FPGA design engineers typically make in their design and provides suggestions and alternatives which can be used as a solution for the same. This document assumes that the reader already